Multiplication unit operating serially by digit and parallel by bit



J. R. BENNETT 3,319,056 MULTIPLICATION UNIT OPERATING SERIALLY BY May 9,1967 DIGIT AND PARALLEL BY BIT Original Filed May 7, 1962 J 12Sheets-Sheet 1 INVENTOR. Mme-s4? Emma-r7 BY 4 M ATIfiAMfKS.

May 9, 1967 J. R. BENNETT 3,319,056

' MULTIPLICATION UNIT OPERATING SERIALLY BY DIGIT AND PARALLEL BY BITOriginal Filed May 7, 1962 12 SheetS-Sheet 2 Q if Q *3 x Q u m k Q g s wa y R w Q i fi w r 5. E & s N U E INVENTOR. LEM/5s A? BENNETT May 9,1967 .1. R. BENNETT MULTIPLICATION UNIT OPERATING SERIALLY BY DIGIT ANDPARALLEL BY BIT l2 Sheets-Sheet 5 J. R. BENNETT MULTIPLICATION UNI May9, 1967 T OPERATING SERIALLY BY DIG'I'I AND PARALLEL BY BIT l2Sheets-Sheet 4 Original Filed May 7, 1962 J. R. BENNETT MULTIPLICATIONUNIT OPERATING SERIALLY BY May 9, 1967 DIGIT AND PARALLEL BY BITOriginal Filed May 7, 1962 12 Sheets-Sheet 5 J. R. BENNETTMULTIPIJICATION UNIT OPERATING SERIALLY BY v May 9, 1967 DIG'IT ANDPARALLEL BY BIT Original Filed'May 7, 1982 l2 Sheets-Sheet 6 J. R.BENNETT MULTIPLIGATION UNIT OPERATING SERIALLY BY May 9, 1967 DIGIT ANDPARALLEL BY BIT l2 heets-Sheet '1 Original Filed May '7, 1962 W vb N mm?r Emm BY v b/w/v d,

May 9,

J. R. BENNETT DIGIT AND PARALLEL BY BIT Original Filed May 7, 1962 12Sheets-Sheet 8 May 9. 1967 Original Filed May 7, 1962 J. R. BENNETTDIGIT AND PARALLEL BY BIT MULTIPLICATION UNIT OPERATING SERIALLY BY 12Sheets-Sheet 9 mww,

ATTOF/V'VS.

12 Sheets-Sheet l0 J. R. BENNETT DIGIT AND PARALLEL BY BIT May 9, 1967MULTIPLICATION UNIT OPERATING SERIALLY BY Original Filed May 7, 1962mmmmhwwh whims E May 9, 1967 J. R. BENNETT 3,319,056

MULTIPLICATION UNIT OPERATING SERIALLY BY DIGIT AND PARALLEL BY BITOriginal Filed May 7, 1962 12 Sheets-Sheet 12 ATTORNEYS.

United States Patent 3,319,056 MULTIPLICATION UNIT OPERATING SERIALLY BYDIGIT AND PARALLEL BY BIT James R. Bennett, Glendora, Califi, assignorto Burroughs Corporation, Detroit, Mich, a corporation of MichiganContinuation of application Ser. No. 192,885, May 7, 1962. Thisapplication Nov. 19, 1965, Ser. No. 513,644 14 Claims. (Cl. 235-159)This invention relates to digital computers and more particularly toimprovements in apparatus for performing multiplication in a digitaldata processor.

This case is a continuation of a previously filed application Ser. No.192,885, filed May 7, 1962, now abandoned, by the same inventor as thispatent application.

Generally, scientific computers have three registers for storing thefull multiplier operand, the full multiplicand operand, and the fullproduct word for performing multiplication. Multiplication is performedby reading out the multiplier and multiplicand operands and storing themin the corresponding registers and then adding the Whole multiplicandoperand to the contents of the product register the number of timesindicated by the magnitude of the multiplier operand. With thisarrangement, separate registers are needed for storing the completeoperands and the complete product. Another prior art arrangementutilizes an accumulator register for the dual purpose of storing themultiplier and the product.

Both of the aforementioned prior art arrangements duplicate storageunits. For example, a product storage field is provided in the memory ofthe computer for storing the complete product. However, information isstored in the product field of the memory only after the multiplicationoperation is complete and a complete product has been obtained. Thus, inthe first example storage is provided for the complete product both inmemory and in the additional product register. Both of theaforementioned prior art arrangements not only have operand fields inthe memory for storing the complete multiplier and multiplicandoperands, but have additonal registers for storing the completemultiplicand and multi plier operands external of the memory.

In a serial computer only one bit of the multiplicand and multiplieroperands are used at any one instant in time to perform multiplication.Additionally, the reading and writing circuits for the memory unit ofmost computer machines are normally used inefficiently in that they areused only about 25% of the total computing time. One reason for theinefiicient use of memory is that operand and product addresses of eachcommand are read out of the memory only once. Also, as discussed above,the product is written only when complete. However, such an arrangementis necessary in scientific computing machines where extremely highcomputing speeds are necessary.

A digital data processor processes data from peripheral data units.Generally data is supplied for processing at a low rate. The rate atwhich peripheral data units receive data is similarly at a low rate. Thespeed with which data is received, processed and shifted back out toother peripheral units is limited, not by computing or processing speed,but by the rate at which data is made available to the processor andread out therefrom. Thus, a digital data processor may reduce the rateat which data is processed as compared with scientific computingmachines and yet overall system speed will remain constant. 1

However, present data processors normally use the scientific computermachine arrangement for performing multiplication even in view of theduplication of equipment and ineflicient use of memory.

In contrast, a specific embodiment of the present invention is amultiplication unit for performing multiplication in much the same Wayas that taught in grammar school. For example, the multiplier andmultiplicand operands are arranged in digits. The low order digit of themultiplier is multiplied times each digit of the multiplicand and foreach multiplicand digit multiplied a corresponding partial product digitis formed. After one multiplier digit has been multiplied times allmultiplicand digits, the next higher order multiplier digit ismultiplied times each digit of the multiplicand. However, in contrast tothe grammar school method of multiplication, the partial product digitof each multiplication is added to the same order partial product digitformed during previous multiplications concurrently with the formingthereof.

Also, in contrast to the prior art multiplication apparatus and methodfor performing multiplication, the present invention allows a dataprocessor to be built with minimum number and size of auxiliaryregisters. Also, the memory of a digital data processor embodying thepresent invention may be used to its maximum efiiciency without makingunnecessary memory accesses.

Additionally, a multiplication unit in one embodiment of the presentinvention operates serially by digit but parallel by bit. Normallyperipheral units supply data to the data processor in the form ofdigits. Therefore, by processing digits of information, themultiplication unit becomes much more compatible with the peripheraldata handling equipment than in computing machines performingmultiplication serially, a bit at a time. Also, operating serially adigit at a time is much faster than operating serially on each bit of aword.

Briefly, a specific embodiment of the present invention comprises amultiplication unit for a data processor including an addressable memorywith multiplier and multiplicand operands arranged in digits and writtentherein. Means is provided for repeatedly reading out of the memory eachof the digits of a multiplicand operand concurrently with the readingout of each digit of the multiplier operand. Means is provided forstoring one multiplier digit and one multiplicand digit read out of thememory. Means is provided for combining the stored multiplier andmultiplicand digits together for developing a partial product digit.Means is provided for writing the developed partial product digit in thememory. Means is provided for reading out of the memory a partialproduct digit concurrently with the developing of the correspondingpartial product digit to be combined therewith. The combining means isadditionally arranged for combining the read out partial product digitwith the corresponding partial product digit being developed fordeveloping a complete partial product digit until a complete productcomposed of partial product digits is written in the memory.

A more complete understanding of the present invention may be obtainedwith reference to the following description of the figures of which:

FIGURE 1 is a pictorial View of a banking system and embodying thepresent invention;

FIGURE 2 is a general block diagram of a multiplication unit for thedigital data processor of FIGURE 1 and embodying the present invention;

FIGURE 3 is a more detailed block diagram of the multiplication unit forthe digital data processor of FIG- URE 1 and embodying the presentinvention;

FIGURES 4A through 4Y are schematic diagrams showing the details of thetiming generator of FIGURE 3;

FIGURE 5 is a wave shape diagram showing the control pulses forsequencing the operation of the memory unit of FIGURES 2 and 3.

FIGURE 6 is a sketch illustrating the word structure f operand andproduct digits used in the multiplication nit of FIGURES 2 and 3.

FIGURE 7 is a sketch illustrating the structure of ommand digits for usein the multiplication unit of IGURES 2 and 3.

FIGURE 8 is a flow diagram illustrating the sequence f operation of thedesignated registers, timing flip-flops nd the memory unit of themultiplication unit of IGURES 2. and 3;

FIGURE 9 is a sketch illustrating the structure of a multiplicationcommand word and the corresponding tates of the command registernecessary to address the ligits of the command along with an example ofa command word;

FIGURE 10 is a sketch showing an example of the op- -.rands and thestorage content of the product field in the memory storage locationsspecified by the multiplication :ornmand word example of FIGURE 9.FIGURE 10 L180 includes a sketch illustrating the storage content of heproduct field at indicated time intervals during the :xecution of thecommand word example of FIGURE 9; and

FIGURE 11, including FIGURES 11A and 11B, is a ".ketch illustrating thesequence of operation of indicated registers and timing flip-flops inthe multiplication unit of FIGURES 2 and 3 while executing the commandword example shown in FIGURE 9 on the operands shown in FIGURE 10.

General description FIG. 1 is a pictorial view of an automaticbookkeeping and accounting system for use in a bank. The banking systemof FIG. 1 does all the collating, calculating and summarizing forbookkeeping and for updating ledger cards normally accomplished bymultiple runs in other automatic banking systems. At the center of thebanking system is a digital data processor 10 which is the nerve centeror central control and processing unit of the banking system. Theprocessor 10 performs all the editing and computation on data enteredinto the banking system. At the left of the processor 10 of FIG. 1 is anadding machine type amount encoder 12 which is used by the proofdepartment of a bank to encode or print account numbers and amountnumbers on incoming cash letters, checks, and customer deposit slips.All the encoding by the encoder 12 is done in Magnetic Ink CharacterRecognition coded characters.

The encoded documents from the encoder 12 are put into a high-speed itemsorter reader 16. The item sorter reader 16 introduces new digits orcharacters of data into the processor 10 for editing and processing. Thesorter reader 16 also sorts and stores documents in one of 13 pocketsprovided in the unit.

At the right of the processor 10 in FIG. 1 is a visual record processor18. The processor 18 processes ledger cards which have visualinformation printed on the front and coded information written onmagnetic stripes on the back side thereof.

A card punch unit 20 is provided at the right of the processor 10 forpunching the coded output information from the processor 10 on papercards. At the left of the processor 10 is a program card reader 22. Theprogram card reader 22 provides the processor 10 with a stored programconsisting of commands for sequencing the operation thereof.

Other details of the banking system shown in FIG. 1 are given in acopending patent application entitled, Data Processing System, assignedto the same assignee as this patent application, bearing the Ser. No.81,149, and filed on Jan. 6, 1961, issued on Jan. 4, 1966 as Patent No.3,228,006.

Refer now to FIG. 2. FIG. 2 is a general block diagram of themultiplication unit used in the digital data processor 10 of FIG. 1.Some of the circuits shown in FIG. 2. Assume that the multiplier operand12 is to be of the processor 10 such as addition and subtraction asdescribed in a copending application entitled, Digital Data Processorassigned to the same assignee as this application, bearing the Ser. No.80,171 and filed on Jan. 3, 1961, now abandoned, a continuation of whichissued as Patent No. 3,274,558.

Before considering the actual circuits of the multiplication unit ofFIG. 2, consider briefly the sequence of steps of multiplication used bythe multiplication unit of FIG. 2. Assume that the multiplier operand 12is to be multiplied times the multiplicand operand 326.

TABLE I Multiplicand 326 Multiplier 12 First partial product digits00652 Second partial product digits 0326 Final product 03912 TABLE IIMultiplicand 326 Multiplier x 12 First partial product 0652 Finalproduct 03912 As indicated in Table I, the grammar school pencil andpaper method of multiplying the operands together is accomplished byfirst taking the low order digit of the multiplier, a digit 2, andmultiplying it times each digit of the multiplicand, digits 32.6,resulting in partial product digits 652. Subsequently, the second digitof the multiplier, a digit 1, is multiplied times each digit of themultiplicand, resulting in another set of partial product digits 326.The two sets of partial product digits are then added together to givethe final product 3912.

The steps of multiplication in the multiplication unit of FIG. 2 arequite similar to that outlined in Table 1. However, instead of writingor storing the partial products for each multiplier digit separately andlater adding the corresponding partial product digits together, thecorresponding partial product digit formed during the multiplication bythe next lower order multiplier digit is added to each. partial productdigit as it is determined and the resultant partial product digit isimmediately written into a memory.

Table II shows an example of the actual steps of multiplication used bythe multiplication unit of FIGS. 1 and 2. As indicated in Table II themultiplier digit 2 is multiplied times the multiplicand 326, giving apartial product of 652 which is written in memory digit by digit as thedigits are forrned. Subsequently, the multiplier digit 1 is multipliedtimes each of the multiplicand digits 326. However, in contrast to thepencil and paper method of multiplication shown in Table I,the resultingpartial product digits 326 are added, as each is determined, directly tothe corresponding partial product digits, in memory, determined duringthe multiplication by the next lower ordered multiplier digit, resultingdirectly in the product 3912 which in turn is written in memory digit bydigit as the digits are formed.

Refer now to the structure of the command words used in the multiplierunit of FIGS. 2 and 3, as illustrated at the upper part of FIG. 9. Itwill become evident in the following discussion that the multiplier unitis a variable field length multiplier, multiplying operands havingvariable numbers of digits or characters. In an actual data processormodel incorporating the present invention, each operand has one up to amaximum of twelve digits. However, for the purpose of explaining theinvention it is assumed that operands have a maximum of nine digits.Each multiplier command contains twelve digits or characters. The digitsof each multiplier command include an order digit three digits forspecifying the address of the most significant digit of the multiplieroperand (a3, a2 and a1), three digits for specifying the address of themost significant digit of a product storage field (c3, c2, and c1) andtwo field length digits (af and bf) which are indicative of the lengthof the multiplicand and multiplier operands.

The multiplication unit of FIG. 2 24 which is arranged with word anddigit storage locations. The memory of the actual data processor modelhas four hundred word storage locations and within each word of storageis twelve digits o-f storage. In order to simplify the description andfor purposes of illustrating the invention, it is assumed that there areonly ninety-nine words of storage. The ninety-nine words of storage inthe memory 24 are numbered 1 through 99. The twelve digits within eachword of storage of the memory 24 are numbered 0 through 11.

As illustrated at the lower part of the sketch of FIG. 9, the commanddigits 0, af, bf, (13, a2, a1, b3, b2, bl, c3, 02, and cl are alwaysstored in the digit storage locations 0 through 11, respectively, of aword of storage in the memory 24. At the middle part of the sketch ofFIG. 9 is an example of the command word stored in the memory wordstorage location 53. As indicated in FLIG. 9, the command word stored inthe word storage 56 has a digit 3 stored in the order (0) position. Anorder digit 3 indicates that the command is a multiplier command asopposed to other commands such as addition comm-ands, etc. The addressof the most significant digits of the multiplicand operand, themultiplier operand, and the product field are 2-0-0, 2-0-3, and 2-0-5,respectively. The length of the multiplicand and multiplier operands are3 digits (af) and 2 digits (bf), respectively. Therefore the mostsignificant digit of the multiplicand operand is stored in digit storageposition 0 of word storage 20, the address of the most significant digitof the multiplier is stored in digit storage position 3 of word storage20 and the address of the most significant digit of the product is to bestored in digit storage 5 of word storage 20. The first and seconddigits of the multiplier and multiplicand operand addresses are used asthe tens and units digits of a word of storage of 12 digits in memory.

Refer now to FIG. 10. FIG. is .a sketch showing an example of thestorage content of the memory storage locations 2-0-0 through 2-0-9. Thesymbol X is used to represent a stored decimal digit which is not usedduring the execution of the multiplier command. As indicated in FIG. 10,the numbering of the digit storage of each word storage, increases fromleft to right, whereas, the order of magnitude of each operand and theproduct field increases, from the least significant digit to the mostsignificant digit, proceeding from right to left. Using the command inFIG. 9 the most significant digit of the multiplicand is stored inaddress 2-0-0 and the multiplicand field is three digits (af) long, themultiplicand operand is stored in the address 2-0-0, 2-0-1 and 2-0-2.Therefore, the multiplicand operand is a decimal number 326. Similarly,the most significant digit of the multiplier is stored in the memoryaddress 2-0-3 and the multiplier operand is two digits (bf) long.Therefore, the multiplier operand is stored in the addresses 2-0-3 and2-0-4 and is a decimal number 12. To be explained in detail, the symbolin front of the number 2 indicates the multiplier operand 12 isnegative. The product field begins with address 2-0-5 and the lengththereof, is equal to the sum of the two multiplicand and multiplierfield length digits (5 digits long). Thus, the product field includesthe address 2-0-5 through 2-0-9.

The method of deriving the address of the least significant digit ofoperands and product fields is important in understanding the operationof the multiplication unit of FIGS. 2 and 3. In order to obtain theaddress of the least significant digit of the multiplier andmultiplicand includes a memory operands, the address of the mostsignificant digit thereof must be added to the corresponding fieldlength digit minus one unit. Thus, in the example of FIG. 9, the addressof the least significant digit of the multiplicand is equal to 2-0-0plus 3 (af) minus 1 or 2-0-2. Referring now to FIG. 10 it will be notedthat the address 2-0-2 is the address of the least significant digit ofthe multiplicand operand. The address of the least significant digit ofthe product field is derived by adding the address of the mostsignificant digit of the product field to the multiplier field lengthdigit (bf) minus one, plus the multiplicand field length dig-it (af)minus one, plus one unit. For example, the address of the leastsignificant digit of the product field for the example of FIG. 9 isequal to 2-0-5, plus 2 minus 1, plus 3 minus 1, plus 1 or 2-0-9. Asindicated in FIG. 10, 2-0-9 is the address of the least significantdigit of the product field.

The above-mentioned data processor model is arranged with seven hits ineach operand and command digit. However, in order to simplify thedescription of the invention, two of the bits may be neglected an-d itis assumed, for purposes of explanation, that these digits only havefive bits. FIG. *6 shows an example of the structure of the operand andproduct digits. As indicated in FIG. 6, the first bit is rep-resented bythe symbol B and is a sign bit. The other four hits are numbered in the8-4-2-1 number code and form the numeric portion of the operand andproduct digits. FIG. 7 shows an example of the structure of the commanddigits. As indicated, the first digit is again represented by the symbolB, however, -bit B of command digits is only included, for purposes ofillustrating the invention, in order to keep all digits with the samenumber of bits. However, in the actual data processing machine this bitis used. The remaining four bits of the command digits are also numberedin the 8-4-2-1 number code and form the numeric portion of the digit.

Refer now to the general block diagram of the multiplier unit shown inFIG. 2. The memory 24 of the multiplier unit is addressed by a commandregister 28 and a memory register 26, hereinafter referred to as the Creg-28 and M reg-26. The C reg-28 is used for fetching the commands orfor addressing the digits of each command stored in the memory 24,whereas the M reg-26 is used for addressing digit storage locations ofthe operand and product fields in the memory 24. Information is read outof the addressed storage locations of the memory 24 a digit at a time.Each digit read out of and to be written into the memory 24 is stored inan information register 30, hereinafter referred to as the I reg-'30.When a command is to be fetched and executed, the C reg-28 firstaddresses the order digit (0) of the command. The addressed order digitis read out of the memory 24 into the I reg-30 and then stored in anorder register '32, herein-after referred to as the O reg-32. If theorder digit is a digit 3 a multiplication cycle of operation iscommenced.

The field length digits (af and by) of the same command are thensequentially addressed by the C reg-28 and read out of the memory 24into the I reg-30 one I after the other. As the field length digits (afand bf) are read out of the memory 24 into the I reg-30 an adder circuit34 subtracts one unit from the magnitude of each one. The modifiedmultiplicand and multiplier field length digits (af minus one and bfminus one) are then stored in two field length registers 36 and38,'respectively, hereinafter referred to as the A; reg-36 and the Breg-38. Subsequently, the C reg-28 addresses the three digits of theaddress of the most significant digit of the multiplier (b3, b2 and b1)of the same command which are read out of the memory 24 and into the Ireg-30, a digit at a time. As the three digits (b3, b2 and b1) of themultiplier address are read out of the memory 24, the adder circuit 34adds the modified multiplier field length digit (bf minus one), theretoand the 7 :sultant modified multiplier address (b3, b2, b1 plus f minusone) is stored in the M reg.26.

As discussed hereinabove, the preceding addition formed 1e address ofthe least significant digit of the multiplier perand. The M reg-26 nowaddresses the memory 24 ausing the least significant digit of themultiplier operand be read out and stored in a multiplier register 42,hereiafter referred to as the B reg-42.

The C reg-28 now addresses the three digits of the ddress of the mostsignificant digit of the multiplicand a3, a2 and al) of the samecommand. The multiplicand ddress digits (a3, a2 and al) are seriallyread out of he memory 24 and the adder circuit 34 adds the modifiednultiplicand field length digit (af minus one) thereto, hereby formingthe address of the least significant digit )f the multiplicand operand(a3, a2 and al, plus a minus me). The address of the least significantdigit of the multiplicand operand is then stored in the M reg.26. the Mreg-26 then addresses the least significant digit )f the multiplicandoperand, causing it to be read out of he memory 24 into the I reg.30 andfinally to be stored n a multiplicand register 40, hereinafter referredto as the k reg-4t).

With the least significant multiplier and multiplicand )perand digitsstored in the A and B regs. and -42, the 3 reg-28 addresses the threedigits of the address of the nost significant digit of the product field(c3, c2, and c1) of the same command, causing the digits to be read outof the memory 24 a digit at a time. As the product field address digits(c-3, c2 and cl) are read out of the memory 24, the adder circuit 34adds the modified multiplier field length digit (bf minus one) theretoand the resultant address '(03, c2, cl plus bf minus one) is stored inthe M reg-26. The adder circuit then automatically adds the modifiedproduct address stored in the M reg.26 to the modified multiplicandfield length digit ((1 minus one) and simultaneously adds one extra unitto the address.

As discussed hereinabove, the resulting product address (03, c2, 01,plus bf minus one, plus a minus one, plus one) is that of the leastsignificant digit of the product field. The resultant address of theleast significant digit of the product field is stored in the M reg-26.

The adder 34 now adds the multiplicand to itself the number of timesindicated by the magnitude of the multiplier digit stored in the Breg.42 and the resultant partial product digit is stored in the Ireg-30. The M reg-26 then addresses the memory 24 with the address forstorage of the least significant digit of the product field and thepartial product digit stored in the I reg.3tl is written in the memory24 in the least significant digit storage location.

A carry counter 44, hereinafter referred to as the C counter-44, keepstrack of any carries formed by the adder 34 during the multiplicationoperation. To be explained in detail hereinbelow, the carry stored inthe C counter-44 is subsequently added to the next higher order partialproduct digit formed.

After storing the first partial product digit, the modified multiplicandfield length digit (af minus one), stored in the A reg.-36, is decreasedby one additional unit (resulting in a modified field length digit of aminus two). The above cycle of operation is now repeated, beginning withreading out the beginning operand addresses (b3, b2, bl and a3, a2, al).The beginning operand addresses (b3, b2, bl and a3, a2, al) are againadded to the corresponding modified field length digits stored in theB,- and the A regs-36 and 38. This results in a multiplicand address ofthe next to the least significant digit of the multiplicand operand (d3,:12, a1 plus af minus two). Thus, the next to the least significantdigit of the multiplicand operand is addressed, read out of the memory24, and stored in the A reg-40. However, since the modified multiplierfield length digit (bf minus one) is the same, the address of the leastsignificant digit of the multiplier operand (b3,

b2, bl minus one) is again formed, causing the least significant digitof the multiplier operand to be read out of the memory 24 and stored inthe B reg-42. The next to the least significant digit of themultiplicand operand is then added'to itself the number of timesindicated by the magnitude of the least significant multiplier digit. Atthe same time any carry, as indicated by the storage content of the Ccounter-44, is added into the partial product digit. The new partialproduct digit is then written in the memory 24. However, it should benoted that the new partial product digit is written into the next to theleast significant position of the product storage field.

The above operation is repeated for each multiplicand digit. When eachof the multiplicand digits have been multiplied, a new multiplier digitis brought out and multiplied times each of the multiplicand digits asoutlined above.

The sequence of operation of the multiplier unit for integrating thepartial product digits formed during the multiplication by the leastsignificant multiplier digit should be noted. The digits of themultiplicand operand are sequentially read out of the memory 24 andstored in the A reg-40. Also, the next to the least significant digit ofthe multiplier operand is read out of the memory 24 and stored in the Breg.42 each time a new multiplicand digit is read out of the memory 24.

The partial product dig-its formed during the multiplication ofmultiplier operand digits, including the next to the least significantmultiplier operand digit and higher order multiplier dig-its must becombined with the partial product digits previously formed and writtenin the memory 24. For example, the partial product digits formed duringthe multiplication of the least significant multiplier digit arearranged and stored in the memory 24 .in accordance with the order ofsignificance of the digits. The partial product digits being formedduring the multiplication of the next to the least significantmultiplier digit must be added to the corresponding partial productdigit formed during the multiplication of the least significantmultiplier digit. See Table 11 wherein the partial product digit 6 isadded to the partial product digit 5 to form the partial product digit 1with a carry of 1. To this end, the multiplier unit of FIG. 2automatically reads out the corresponding partial product digit formedduring the multiplication of the least significant multiplier digit andstores the digit in the I reg.3tl. Any carry from a previousmultiplicand, indicated by the state of the C counter-44, is added tothe partial product digit stored in the I reg-30. This is done beforethe actual steps of multiplication are commenced. The actual steps ofmultiplication are then commenced wherein the multiplicand operand digitstored in the A reg-40 is added to the contents of the I reg-30 thenumber of times indicated by the magnitude of the next to the leastsignificant multiplier digit stored in the B reg-42. When themultiplication of a multiplicand digit is completed, the resultantpartial product digit in the sum of the partial product digit resultingfrom multiplying the multiplier and multiplicand operands, the partialproduct digit read out of the memory 24 and any carry, and is stored inthe I re-g.-30. The resultant partial product digit is then written inthe memory 24 in the same position of the product field as the partialproduct digit read out of the memory 24 and stored in the I register-30.

The multiplication of the other digits of the multiplier operand andadding in the corresponding previously formed partial product digits isperformed in a similar manner. Details of the circuits for performingthe multiplication are explained hereinbelow in the sections dealingwith the detailed description of the circuits and operation.

Detailed description of circuits With the general block diagram ofFIGURE 2 in mind, refer now to the detailed block diagram of themultiplier shown in FIGURE 3.

Before considering the other circuits of the multiplier of FIGURE 3, itshould be noted that a timing generator 45 is provided for sequencingthe operation of the various gates, registers and flip-flop circuits ofFIGURE 3. One circuit of importance to each of the other circuits ofFIGURE 3 is a clock pulse generator 47 shown in dashed lines within thetiming generator 45. Clock pulses de veloped by the generator 47 areapplied to each of the registers, flip-flop circuits, counters and thecontrol for memory 24 of FIGURE 3 as well as timing flip-flops withinthe generator 45. The clock pulses synchronize the change in state ofeach of these circuits unless otherwise specified.

Flip-flop circuits have two stable states of operation. These stablestates will be referred to hereinafter as the l and states. Flip-flopsalso have two inputs for controlling the states into which a clock pulsecauses them to be set. Throughout the following discussion a controlsignal is referred to as the necessary signal for controlling thetriggering of the flip-flops. Control signals at set and reset inputs ofthe flip-flops cause them to be triggered into 1 and 0 states by clockpulses. A control signal at both the set and reset circuits of aflip-flop cause it to reliably change states at the occurrence of aclock pulse.

Memory 24 The memory 24 is a coincident current magnetic core memoryunit. The addressing lines for the memory 24 are connected to the gates46 and 48. The input and output information circuits of the memory 24are connected to gates 50 and 52 respectively. The coincident currentmagnetic core memory 24, as already pointed out in the generaldescription has ninety-nine work storage locations and within each Wordof storage, twelve digits of storage. Each digit storage location hasstorage for five "bits of information.

A memory timing generator 54 is connected to the input of the memory 24.The memory timing generator 54 has three output circuits at which outputpulses are developed in response to clock pulses. FIGURE 5 shows thesequence with which pulses are developed by the memory timing generator54 and their relative pulse lengths. Each time a clock pulse isdeveloped the generator 54 develops a read pulse (RP). During the readpulse, a short strobe pulse (SP) is developed. After the read pulse (RP)and strobe pulse (SP) a write pulse (WP) is developed. The generator 54may be a conventional timing generator using delay lines or a time pulsedistributor using gating circuits such as that described beginning onpage 307 of the book entitled Digital Computer Fundamentals by Thomas C.Bartee, published by the McGraw-Hill Book Company, Inc., 1960.

The output circuits of the generator 54 at which the read pulse (RP) andwrite pulse (WP) are developed, are connected to the coincident currentcore memory 24. The output at which strobe pulse (SP) is developed, isconnected to the input of the I reg.-30.

The memory 24 is responsive to the read pulse (RP) for reading out thebinary bits in parallel, representing a digit stored in the storagelocation addressed by signals from either the gate 46 or the gate 48.Each group of signals read out of memory 24 is applied to the input ofthe gate 52 in parallel. The gate 52 is responsive to a control signalon a read memory line 52a for coupling the digit of signals at the inputthereof to the input of the I re g.-30 in parallel for storage therein.

The memory 24 is also responsive to a write pulse (WP) developed by thegenerator 54 for writing a digit of signals applied at the input thereofby the gate 50. The digit is written in the digit storage locationspecified by address signals from either the gate 46 or the gate 48. Thegate 50.is responsive to a control signal on a write memory line 50a forcoupling the output of the I reg.30 to the input of the memory 24 forallowing the digit 10 stored therein to be written in the memory 24.Coincident current magnetic core memories are -well known in thecomputer art, therefore, other details of the memory 24 will not begiven other than making reference to chapter 8, entitled Magnetic CoreStorage in the book entitled Digital Computer Components and Circuits byR. K. Richards published by D. Van Nostrand Company, Inc., in February1958.

I register-30 The I reg-30 is the input and output information registerof the memory 24. Each digit to be written in the memory 24 is firststored in the I reg-30. Also, each digit read out of the memory 24 isstored in the I reg-30 before being transferred to other circuits in themultiplication unit of FIGURE 3.

The I reg-30 has five flip-flop circuits. The five flipfiops of the Ireg-30 are represented by the symbols IB, I8, I4, I2 and II. Theflip-flop IB is a sign flip-flop for storing a signal indicative of thesign of the digit stored in the I reg-30. The flip-flops I8, I4, I2, andI1 form the numeric portion of the I reg-30 and store the numericportion of digits. The numbers assigned to the flip-flops of the numericportion of the I reg.30 are coded in 8421 number code. The numericflop-flops in a 1 state indicate the magnitude of the digit stored inthe register. Thus, if 14 and I1 are in a 1 state the I reg.- 30 isstoring a digit 5. When the IB register is in 1 and 0 states the Iregister is storing negative and positive digits, respectively.

In addition to the connection to the gates 52 and 50 the I register-30has its output circuit connected to gates 61, 63, 64, 65, 66 and 68 andits input circuit connected to gates 62, 120, 122 and 124. The I reg.30also has control lines 30a, 30b and the SP output circuit of the memorytiming generator 54 connected thereto.

The gate 62 has its input circuit connected to the output of the adder34. The gate 62 is responsive to a control signal on a control line 62afor coupling the output of the adder 34 to the input of the I reg-30 inparallel.

To be explained in the section dealing with the timing generator 45, thecomputer 10 steps through a series of states in executing each commandincluding the multiplication command. The timing generator 45 has outputcircuits corresponding to these states designated PC-l through PC-21.The gates 120, 122 and 124 have control lines connected to the PC-16,PC-15 and PC-14 output lines of the timing generator 45.

A clock pulse in coincidence with signals applied to the I reg.-30 bythe gates 62, 120, 122 and 124 cause the signals to be stored in theflip-flops of the I reg.30.

Similarly, the gate 52 provides signals to the I reg-30. However, incontrast to the signals from the gate 62 which are read in synchronismwith clock pulses the signals from the gate 52 are stored in theflip-flops of the I reg-30 in response to a strobe pulse (SP) from thegenerator 54.

A signal on the line 30a referred to hereinafter as the set 1:0 line 30ain coincidence with a clock pulse causes each of the flip-flops in the Ireg-$0 to be set to a 0 state. A signal on the line 3012, hereinafterreferred to as the .set I b line 30b, in coincidence with a clock pulsesets the IB flip-flop into a 1 state.

The gates 61 and 63 have -a single line output circuit at which acontrol signal is developed whenever the flipflops of the I reg-30 arein states representing digits 3 and '0 respectively.

0 Register-32 The gate 65 has a control input circuit connected to thePC-l output circuit of the timing generator 45. The 0 reg-32 has itsinput circuit connected to the output circuit of the gate 65. A controlsignal at the PC-l output circuit of generator 45 causes the gate 65 tocouple the output of the I reg.30 to the input of the 0 reg-65, whichstores the digit of signals in parallel stored in the I reg-30 at theoccurrence of thenext clock pulse.

Til

A register-40 The A reg-40 has four flip-flops represented by thesymbols A8, A4, A2 and A1, which are number coded in the 842l numbercode as the I reg-30. The A reg.- 40 has information input and outputcircuits connected to the gate 64 and a gate 70, respectively. The Areg.4il also has an input control circuit connected to a set A= line40a.

The gate 64 has its control circuit connected to the PC-11 outputcircuit of the timing generator 45. A control signal at the PC-11 outputcircuit of the generator 45 causes the gate 64 to couple the outputcircuit of the I regto the input circuit of the A reg.40. The digit ofsignals stored in the I reg-30 is stored in the A reg-30 at theoccurrence of a clock pulse when a control signal is applied to gate 64.Gating circuits (not shown) of the A regare also provided and areresponsive to a signal on the set A= 0 line 40a in coincidence with aclock pulse for resetting each of the flip-flops thereof into a 0 state.

B register-42 The B reg-42 has four flip-flops designated B8, B4, B2,and B1 similar to the A reg-40. The flip-flops of the B reg-42 are alsonumber coded in the 8-4-2-1 number code similar to the I reg-3w. Thegate 68 has an output circuit connected to the input of the B reg.42.The B reg-42 has an output circuit connected to the input of two gates74 and 76.

The gate 68 has a control line connected to the PC-7 output line of thegenerator 45. The gate 68 causes the numeric portion of the digit storedin the I reg-30 to be stored in the B reg-42 whenever a control signalis applied on the control line thereof in coincidence with a clockpulse.

Gating circuits (not shown) of the B reg-42 are responsive to a controlsignal on a count -1 line 42a in coincidence with a clock pulse forcausing the B reg.42 to operate as a counter and count the magnitude ofthe digit stored therein down one unit.

Refer now to the gates 74 and 76. The gate 74 is responsive to the stateof the B reg.42, wherein each of the flip-flops therein are in a 0"state for developing a control signal at an output line represented bythe symbol B=O. The signal circuit 76, in contrast to the signal circuit74, is responsive to a non 0 state of any one of the flip-flops of the Bregister-42 for developing a control signal at an output linerepresented by the symbol B =0.

Adder 34 The adder 34 has two digit information input-circuitsdesignated as the X and the Y inputs. The X information input circuit ofthe adder 34 is connected to the output of the gate 66. The Yinformation input circuit is connected to the output of the gate 70 andgates 80, 82, 84 and 86. The adder 34 also has a numeric output circuitconnected to the input of gates 88, 90, 92, 94, 96 and the gate 62.

The X input circuit of the adder 34 has four input circuits representedby the symbols X8, X4, X2, X1 also numbered in the 84-2l number code.Similarly, the Y input circuit and the Z output circuit of the adder 34have four circuits represented by the symbols Y8, Y4, Y2, Y1 and Z8, Z4,Z2, Z1 and numbered in the 8-4-21 number code. Whenever a control signalis applied on a control line 66a of the gate 66, an output circuit ofthe correspondingly numbered flip-flops of the I reg-30 are coupled tothe input circuits X8, X4, X2, X1. Similarly, whenever control signalsare applied to the PC-19 and P c-18 output lines of the generator 45,correspondingly numbered flip-flops of the A reg-40 and the C counter44, respectively, are coupled to the input circuits Y8, Y4, Y2, Y1.Alos, a control signal applied to the gates 84 and 86 causecorrespondingly numbered flip-flops of the Bf reg-38 and the A reg-36,respectively, to be coupled to the input circuits Y8, Y4, Y2, Y1 of theadder 34.

The adder circuit 34 also has a carry input line connected to the outputcircuit of a carry flip-flop represented by the symbol Ca. The addercircuit 34 also has two output lines represented by the symbols CL andCL for indicating a carry-out from any addition performed thereby. Theoutput lines CL and CL are connected to an input circuit of the timinggenerator 45.

The adder 34 has gating circuits (not shown) for adding decimal codedsignals together applied at the X and Y input circuits and forgenerating output signals at the Z8, Z4, Z2, Z1 output circuits whichrepresent the decimal sum. The adder 34 develops a control signal on theCL line whenever the sum of the numbers represented by the decimal codedsignals applied at the X and Y input circuits is greater than 9, therebyindicating a carry out. A control signal is developed on the CL line ofthe adder 34 whenever the sum of the numbers represented by the codedsignals applied at the X and Y input circuits is equal to or less than9, thereby, indicating no carry out.

The adder 34 is arranged in response to the 1 state of the carryflip-flop Ca for adding one extra decimal digit into the sum of thenumbers represented by the coded signals applied at the X and Y inputsof the adder 34.

The adder is a conventional full decimal adder for signals coded in the8-4-2-1 number code such as the one shown and described starting on page2.10 of the book entitled, Arithmetic Operations in Digital Computers byR. K. Richards, published by D. Van Nostrand Company, Inc., in 1955.

The generator 45 has gating circuitry for selectively setting the Caflip-flop into a 1 state in response to a control signal on the CL lineof the adder 34. Details of the gate of the generator 45 for controllingthe setting of the Ca flip-flop to a 1 state will be described in detailin connection with the description of the timing generator 45. The resetinput circuit of the Ca flip-flop for setting it into a 0 state isconnected to the CP output circuit of the timing generator 45.

The input of the gate is connected to the output circuit of a radix 1circuit 98. The circuit 98 is called the radix 1 circuit to indicatethat it continuously develops a four bit output signal representing theradix of the decimal number system minus one or nine. When a controlsignal is applied on a control line 80a of the gate 80 the output of theradix -1 circuit 98 is coupled to the Y input of the adder 34.

The operation of the adder 34 when the radix 1 circuit 98 is coupled tothe Y" input can best be illustrated by an example. Consider theoperation of the adder 34 when signals representing decimal digits areapplied to the X input. The sum of 9 and l is 0 with a carry out. Thus,the adder 34 develops signals representing decimal numeric digit 0 witha carry or control signal on the CL line. Thus, by ignoring the carrysignal the adder 34 has subtracted 1 from 1 leaving 0 as the remainderat the numeric output of the adder 34.

C counter-44 The C counter-44 is provided for keeping track of the carrysignals developed by the added 34 during the multiplication of each ofthe multiplier and multiplicand digits. The C counter-44 has an outputcircuit connected to the input of the gate 82.

The C counter-44 has four flip-flop circuits represented by the symbolsCO8, CC4, C02,.and CC1, and numbered in the 842 l number code as the Ireg.3ll.

The C counter-44 has gating circuits (not shown) which are responsive toa signal on a set=0 line 44a in coincidence with a clock pulse forsetting each of the flipflops thereof into a 0 state. The C counter-44is also responsive to a signal on a set=1 line 44b in coincidence with aclock pulse for setting the CC1 flip-flop into a 1 state and each of theother flip-flops into a "0" state. Additionally, the gates of the Ccounter44 are responsive to a signal on a count +1 line 44c in coin- 13cidence with each clock pulse for counting and increasing the state ofthe carry counter one decimal unit.

A and B field length registers-36 and 38 The A reg-36 has an inputcircuit connected to the output of the gate 90. The output circuit ofthe Af reg-36 is connected to the input circuit of the gate 86 and theinput circuits of gates 108, 110, 112, and 114.

The A; reg.-36 has four flip-flop circuits represented by the symbol-s AS, A 4, A 2, and A l, also numbered in the 842-1 number code as the Ireg-30. Whenever the gate 90 receives a control signal on the PC-3output line of the generator 45 the numeric output circuit of the adder34 is coupled to the input of the A reg.36. The following clock pulsecauses the coded output signals of the adder 34 to be stored in theflip-flops of the A reg-36.

Gating circuits (not shown) are also provided in the A reg.-36, and areresponsive to a signal on a set= line 36a for triggering each of theflip-flops thereof into a 0 state at the occurrence of a clock pulse.The gating circuits of the A reg.-36 are also responsive to a signal ona set=15 line 36b in coincidence with a clock pulse for triggering eachof the flip-flops thereof into a 1 state, thereby causing the A reg-36to represent a decimal number 15. A signal on a count line 360 incoincidence with a clock pulse causes the state of the A; reg-36 tocount down one state and thereby reduce the stored digit one decimalunit. When the A reg-36 is in state 0 and a count signal is applied onthe count line 111, the register is set to represent a decimal number15.

The B: reg-38 is similar to the A reg.3 6 and has four flip-flopsrepresented by the symbols B S, B 4, B 2 and Bfl- The Bf reg-38 has aninput circuit connected to the output circuit of the gate 88. The outputcircuit of the B; reg-38 is connected to the input circuit of the gate84 and the input circuits of gates 1'16 and 118.

The signals developed at the numeric output circuit of the adder 34 arecoupled to and stored in the B reg-38 by the gate 88 at the occurrenceof a clock pulse whenever a control signal is developed on the PC2output line of the generator 45. Gating circuits (not shown) of the Bfreg-38 are also responsive to a signal on a set=0 line in coincidencewith a clock pulse for triggering each of the flip-flop circuits thereofinto a 0 state The set-=0 line is connected to the PC-21 output circuitof the generator 45. A signal on a count -1 line 38a in coincidence witha clock pulse causes the gating circuits of the B; reg-38 to count theregister down one state and reduce the digit stored therein one decimalunit.

The gating circuits 108, 110, 112, 114, i116 and 118 are arranged fordeveloping a control signal indicative of certain states of theregisters 36 and 38. The gating circuit -108 develops a control signalwhenever the A reg-36 is storing a digit zero (all of the flip-flops inthe A reg-36 are in a 0 state). The gating circuit 110 develops acontrol signal whenever the A reg-36 is not storing a digit zero (one ormore of the flip-flops of the A; reg-36 is in a "1 state). The gatingcircuit 112 develops a control signal whenever a decimal number 15 isstored therein (all'of the flip-flops of the A reg-36 are in a 1 state).The gating circuit 114 develops a con trol signal whenever the A: reg-36is not storing a decimal number 15. The gating circuit 116 develops acontrol signal whenever a digit zero is stored in the B; reg-38 (all ofthe flip-flops of the B: reg-38 are in a 0 state). The gate 118 developsa control signal whenever the B reg.3=8 is not storing a digit zero (oneor more of the flip flops of the B reg-38 are in a I state).

M register-26 The M reg-26 has three sections designated; the hundreds(h) sections, the tens '(t) section, and the digits (d) section. Each ofthe three sections of the M reg-26 have four flip-flops which, similarto the I reg-30, are

numbered in the 8-4-2-1 number code. The hundreds (h) section of the Mreg-26 has an input circuit connected to the output of the gate 96 andan output circuit connected to an input circuit of the gate Similar tothe hundreds (11) section, the tens (t) section has an input circuitconnected to the output circuit of the gate 94 and an output circuitconnected to the input circuit of the gate 122. The digits (d) sectionof the M reg-26 has an input circuit connected to an output circuit ofthe gate -92 and an output circuit connected to the input of the gate124.

The gates 96, 94 and 92 are responsive to control signals on controllines 96a, 94a and 92a, respectively, for storing the output signaldeveloped at the numeric output circuit of the adder 34 in the hundreds,tens, and digits sections, respectively, of the M reg.26.

Gating circuits (not shown) of the M reg-26 are responsive to a controlsignal on a set=0 line, connected to the PC-21 output circuit of thegenerator 45, in coincidence with a clock pulse for automaticallysetting all of the flip-flops thereof into a 0 state.

The gate 46 couples the outputs of all of the sections of the M reg-26to the addressing circuits of the memory 24 in response to a controlsignal on a control line 46a.

C register-28 Similar to the M reg-26, the C reg-28 is arranged in threesections, referred to as the hundreds (h), the tens (t), and the digits(d) sections. The output of all of the three sections of the C reg- 28are connected to the input of the gate 48. A signal on a control line48a of the gate 48 causes the gate 48 to couple the outputs of the Creg-28 to the addressing circuits of the memory 24.

To be explained in the following discussion, the hundreds (h) and thetens (t) sections of the M reg-26 and the C reg-28 address the wordstorage locations in the memory 24. The digits (d) section of the Mreg-26 and the C reg-28 address the digit storage locations within eachword storage location.

The C reg-28 contains gating circuits (not shown) which are responsiveto a signal on the count line for advancing the hundreds (h) and tens(t) sections of the C reg-28 one decimal digit. The hundreds (h) andtens (1) sections of the C reg.28 are arranged to count in the decimalnumber system and have 100 possible states. The states of the hundreds(h) and tens (t) sections of the C. reg-28 are referred to as states 0through 99. A signal on the PC21 output line of generator 45 incoincidence with a clock pulse, causes the hundreds (h) and the tens (t)sections of the C reg.28 to count up one decimal unit.

Set lines represented by the general symbol are provided for controllingthe states of the digits section of the C reg-28. For purposes ofexplanation of the multiplication unit, it is assumed that the digitssection of the C reg.-28 has twelve possible states of operation,referred to as states 0 through 11. The set lines 130 are shown inFIGURE 4-V and as indicated, there is a set line for each of the states0 through 11 of the digits (d) section of the C reg-28. A control signalon a set line causes the digits section to be set to the correspondinglynumbered state.

Timing Generator 45 The timing generator 45 contains the gatingcircuits, counters, and timing flip-flops which are not otherwise shownfor controlling and sequencing the operation of the multiplication unitof FIGURE 3. The circuits of the timing generator 45 are shown inFIGURES 4-A through 4-Y.

15 ?C21 referred to hereinabove. When the counter 132 s in a particularstate, a control signal is developed on the :orrespondingly numberedoutput line.

In the actual model of the digital computer, the program counter 132 iscomposed of a number of control flipflops and gating circuits. However,for purposes of illustration and in order to simplify the explanation ofthe operation, the program counter 132 is shown having counters 134,135, 136, 137, 138, 139 and 148. Each of the counters of the programcounter 132 have a state. In addition, the counter 134 has a state 1;the counter 135 has states 2 through 7; the counter 136 has states 8through 14; the counter 137 has states 15 through 18; the counter 138has a state 19; the counter 139 has a state 20; and the coutner 140 hasa state 21. The output circuits PC1 through PC21 are connected to theoutputs of the counters 134 through 140 having the correspondinglynumbered states. Additionally, the counters of the program counter 132have set circuits which are responsive to an applied control signal forsetting the counters from state 0 into the designated state. Once acounter of the program counter 132 is in a state other than state 0 thesucceeding clock pulses cause the counters to count through theincreasingly numbered states. When a counter is in its highest numberedstate, the next clock pulse causes it to count back to state 0, where itremains until another set control signal is received. All of thecounters 134, 135, 136, 137, 138, 139 and 140, except one, are in a 0state during operation.

The counter 134 has a set=1 circuit connected to the P021 output circuitof the program counter 132.

The counter 135 has three set circuits referred to as set=2, set=3 andset=4 circuits and are connected to the output circuits of and gates142, 144 and 146, respectively.

The and gate 142 has input circuits connected to the PC1 output circuitof the program counter 132 and the [:3 output circuit of the gate 61(see FIGURE 3). The and gate 144 has input circuits connected to thePCZIP, the A =15 and the B O output circuits of the program counter 132,and the gates 112 and 118 (see FIGURE 3). The and gate 146 has its inputcircuits connected to the PC20, the A;#() and the Af 15 output circuits(see FIGURE 3).

The counter 136 has two set circuits called set=8 and set: 12 inputcircuits and are connected to the output circuits of an and gate 148 andan or gate 150.

The input circuits of the and gate 148 are connected to the PC7 outputcircuit of the counter 132 and an output circuit of a signal invertercircuit 152. The input circuit of the inverter circuit 152 is connectedto the output circuit of an and gate 154. The input circuits of the orgate 150 are connected to the output circuit of the and gate 154 andanother and gate 156. The and gate 154 has its input circuits connectedto the PC7, T and 1:0, output circuits of the program counter 132, atiming flip-flop T (see FIGURE 4W) and gate 63 (see FIGURE 3). The andgate 156 has its input circuits connected to the PC20 and A =0 (seeFIGURE 3) output circuits.

The counter 137 has input circuits referred to as set=15 and set=18circuits connected to the output circuits of and gates 158 and 160. Theand gate 158 has its input circuits connected to the PC14 and the A #l(see FIGURE 3) output circuits. The and gate 160 has its input circuitsconnected to the PC14 and A -15 (see FIGURE 3) output circuits.

The counter 138 has a control circuit referred to as a set: 19 inputcircuit connected to an or gate 162. The or gate 162 has input circuitsconnected to and gates 164 and 166. The and gate 164 has its inputcircuits connected to the PC18 and B 0 (see FIGURE 3) output circuits.The and gate 166 has its input circuits connected to the B0 (see FIGURE3) and PC-19 out- 16 put circuits. The counter 139 has a set=20 circuitconnected to an or gate 168. The or gate 168 has its input circuitsconnected to and gates 170 and 172. The and gate 170 has its inputcircuits connected to the PC19 and the B=0 (see FIGURE 3) outputcircuits. The inputs of the and gate 172 are connected to the PC18 andB=O output circuits.

The counter 140 has a -set=21 input circuit connected to an and gate174. The and gate 174 has its input circuits connected to the PC20, A=15, and B =0 (see FIGURE 3) output circuits.

Refer now to FIGURES 4B, 4C and 4-D which show the gates of the timinggenerator 45 for developing control signals for the gates 50, 46 and 48of FIGURE 3. The Write memory line 50a to the gate 50 of FIGURE 4B isconnected to a signal inverter 176. The inverter 176 is connected to anor gate 178. The or gate 178 has input circuits connected to the PC15through PC19 and PC21 output circuits of the program counter '132. Thecontrol line 46a to the gate 46 is connected to an or gate .149 ofFIGURE 4-C. The or gate 149 has inputs connected to the PC7, PC11, PC18and PC-20 output circuits of the program counter 132. The control line48a to the gate 48 is connected to an or gate 151 of FIGURE 4D. The orgate 151 has inputs connected to the output circuits PC1 through PC-6,PC-8, PC-9, PC-10, PC12, PC-13 and PC- 14.

Refer now to FIGURE 4E which shows the gates for developing controlsignals on the set lines to the I reg.30. The set IB=1 line 30b isconnected to the input circuit of an and gate 184. The and gate 184 hasinput circuits connected to the PC19, T T and B==O output circuits ofthe program counter 132, the flip-flops T (see FIGURE 4W) and T (seeFIGURE 4Y) and the gate 74 (see FIGURE 3).

The set 1:0 line 30a is connected to a signal inverter circuit 186. Theinverter circuit 186 has its input circuit connected to an or gate 188.The or gate 188 has its input circuits connected to the PC14, PC15,PC16, PC18 and PC19 output circuits of the program counter 132.

FIGURE 4-F shows the circuits for developing control signals on the readmemory line 52a to the gate 52 (see FIGURE 3). The read memory line52ais connected to a signal inverter 190. The inverter 190 has its inputcircuit connected to an or gate 192. The or gate 192 has its inputcircuit connected to the PC15, PC16, PC17, PC19, PC20, PC21 outputcircuits of the program counter 132 and the output circuit of an andgate 194. The an gate 194 has its input circuits connected to the PC18output circuit and the output circuit of an or gate 196. The or gate 196has its input circuits connected to the T and A 15 output circuits ofthe timing flip-flop T (see FIGURE 4X) and the gate 112 (see FIGURE 3).

FIGURE 4G shows a gate for developing control signals on the controlline 62a to the gate 62. The control line 62a is connected to an or gate193' which has input circuits connected to the PC18 and PC-19 outputcircuits of the program counter 132.

Refer now to FIGURES 4H, 4I, 4I, 4-K, and 4L which show the gates forapplying control signals on the control lines to the gates 66, 80, 86,and 84 and for applying the set signal to the carry flip-flop Ca. Thecontrol line 66a to the gate 66 is connected to a gate 274 of FIGURE 4H.The gate 274 has inputs connected to the PC-2 through PC-6, the PC-Sthrough PC10 and the PC-12 through PC-19 output circuits of the programcounter 132.

The control line 80a to the gate 80 is connected to an or gate 270 ofFIGURE 4E. The or gate 270 has inputs connected to the PC2 and PC-3output circuits of program counter 132.

The control line 86a to the gate 86 is connected to an Or gate 272. Theor .gate 272 has input circuits

1. A MULTIPLICATION UNIT FOR A DIGITAL COMPUTER COMPRISING: MEMORY MEANS FOR STORING OPERANDS ARRANGED IN DIGITS, AND COMMAND SIGNALS, EACH COMMAND INCLUDING END DIGIT ADDRESSES OF BOTH A MULTIPLIER OPERAND AND A MULTIPLICAND OPERAND, AND THE END DIGIT ADDRESS OF A PRODUCT FIELD; MEANS FOR REPEATEDLY READING OUT OF THE MEMORY MEANS THE END MULTIPLIER AND MULTIPLICAND OPERAND ADRESSES OF A COMMAND; MEANS RESPONSIVE TO A READOUT END MULTIPLIER OPERAND ADDRESS FOR FORMING A CORRECTED ADDRESS FOR EACH OF THE DIGITS OF THE MULTIPLIER OPERAND IN SEQUENCE; MEANS RESPONSIVE TO A READ OUT END MULTIPLICAND OPERAND ADDRESS FOR FORMING A CORRECTED ADDRESS OF EACH OF THE DIGITS OF A MULTIPLICAND OPERAND AT LEAST ONCE FOR EACH DIFFERENT ADDRESS OF THE MULTIPLIER OPERAND; MEANS FOR READING OUT OF THE MEMORY MEANS EACH OF THE DIGITS OF THE OPERANDS IN SEQUENCE AS SPECIFIED BY THE CORRECTED END OPERAND ADDRESSES; MEANS FOR STORING AT LEAST ONE DIGIT OF BOTH THE MULTIPLIER AND MULTIPLICAND OPERANDS READ OUT OF THE MEMORY MEANS; ARITHMETIC MEANS FOR COMBINING THE STORED OPERAND DIGITS AND FOR FORMING A PARTIAL PRODUCT DIGIT AND AN INDICATION OF ANY RESULTING CARRY; MEANS FOR STORING THE CARRY INDICATION; MEANS FOR REPEATEDLY READING OUT OF THE MEMORY MEANS THE END PARTIAL PRODUCT ADDRESS OF THE SAMD COMMAND; MEANS RESPONSIVE TO THE READ OUT END PARTIAL PRODUCT ADDRESS FOR SEQUENTIALLY FORMING CORRECTED PRODUCT ADDRESSES CORRESPONDING TO THAT FOR STORAGE OF EACH PARTIAL PRODUCT DIGIT; MEANS RESPONSIVE TO THE CORRECTED PRODUCT ADDRESSES FOR WRITING EACH OF SAID PARTIAL PRODUCT DIGITS IN THE CORRESPONDING MEMORY MEANS STORAGE LOCATION; MEANS RESPONSIVE TO THE CORRECTED PRODUCT ADDRESSES FOR SELECTIVELY READING OUT OF THE CORRESPONDING STORAGE LOCATION OF THE MEMORY MEANS A CORRESPONDING PARTIAL PRODUCT DIGIT STORED THEREIN, SAID COMBINING MEANS ADDITIONALLY BEING ARRANGED FOR SELECTIVELY COMBINING A STORED CARRY INDICATION AND A PARTIAL PRODUCT DIGIT READ OUT OF THE MEMORY MEANS WITH THE MULTIPLIER AND MULTIPLICAND DIGITS BEING COMBINED TO THEREBY CAUSE A COMPLETE PARTIAL PRODUCT DIGIT TO BE FORMED UNTIL A COMPLETE PRODUCT COMPOSED OF PARTIAL PRODUCT DIGITS IS WRITTEN IN THE MEMORY MEANS. 